The present invention relates to semiconductor integrated circuits, and methods of designing and making the circuits. More particularly, the present invention relates to failure analysis of an on-chip memory provided in a large-scale integrated system or an on-chip memory and a SRAM (Static Random Access Memory) produced in a new process.
Failure analysis of a cache memory provided in a large-scale integrated system and an on-chip memory produced in a new process at the beginning of its manufacture is complicated and requires much time and hence hinders an early start-up of the manufactured article. Such failure analysis is made by changing an activation timing of a sense amplifier and acquiring a fail bit map, but it is difficult to specify the causes of the failures and to start up the article early. Recently, it has been tried to directly measure the memory cell""s current and irregular AC characteristics of sense amplifier offset voltages within the chip to thereby start up the article early. This method, however, requires designing and making a TEG (Test Element Group) by way of trial, which increases the cost.
A well-known technique to solve this problem is disclosed in U.S. Pat. No. 6,081,465 issued to Wang et al. This reference discloses a circuit for controlling a potential of a bit line with a new switch externally to directly measure an AC characteristic, for example, of a memory cell current in the manufactured article itself to thereby facilitate its failure analysis.
In this prior art, however, it is necessary to add the switch newly to the bit line, which invites increases in the memory area and access time for the memory. The access to the memory is possible only in units of a column, and a signal to select a column is needed, which further increases the memory area.
According to one aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a plurality of memory cells (CELL); a pair of bit line (CBL0) and complementary bit line (BB0) connected to the plurality of memory cells; a precharging P-channel type MOS transistor (MP5) for connecting the bit line (BL0) to a first power voltage line (VDD); a second precharging P-channel type MOS transistor (MP6) for connecting the complementary bit line (BB0) to a second power voltage line (VDD1); an equalizing P-channel type MOS transistor (MP7) for connecting the bit line (BL0) and the complementary bit line (BB0); a P-channel type MOS transistor (MP11) for connecting the bit line (BL0) to a sense amplifier circuit (107); and a P-channel type MOS transistor (MP12) for connecting the complementary bit line (BB0) to a sense amplifier circuit (107), wherein control signals for the precharging P-channel type MOS transistors (MP5 and MP6) are separated from a control signal for the equalizing P-channel type MOS transistor (MP7) so that the bit lines (BL0, BB0) are supplied with corresponding separate voltages.
The first and second power voltages (VDD) and (VDD1) lines are at the same voltage level in a normal operating period. Those power voltage lines are connected to different voltage levels in the failure analysis, and independent voltage levels are applied to the bit line (BL0) and the complementary bit line (BB0) to thereby measure an offset voltage of the sense amplifier and a read current flowing in the memory cell.